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| MCP6291/2/3/4/5 1.0 mA, 10 MHz Rail-to-Rail Op Amp Features * * * * * * * * Gain Bandwidth Product: 10 MHz (typ.) Supply Current: IQ = 1.0 mA Supply Voltage: 2.4V to 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in Single, Dual and Quad Packages Single with Chip Select (CS) (MCP6293) Dual with Chip Select (CS) (MCP6295) Description The Microchip Technology Inc. MCP6291/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 10 MHz Gain Bandwidth Product (GBWP) and a 65 phase margin. This family also operates from a single supply voltage as low as 2.4V, while drawing 1 mA (typ.) quiescent current. In addition, the MCP6291/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. This family of operational amplifiers is designed with Microchip's advanced CMOS process. The MCP6295 has a Chip Select input (CS) for dual op amps in an 8-pin package. This device is manufactured by cascading the two op amps, with the output of op amp A being connected to the non-inverting input of op amp B. The CS input puts the device in a Low-power mode. The MCP6291/2/3/4/5 family operates over the Extended Temperature Range of -40C to +125C. It also has a power supply range of 2.4V to 5.5V. Applications * * * * * * Automotive Portable Equipment Photodiode Amplifier Analog Filters Notebooks and PDAs Battery-Powered Systems Available Tools * SPICE Macro Model (at www.microchip.com) * FilterLab(R) Software (at www.microchip.com) Package Types MCP6291 PDIP, SOIC, MSOP NC 1 VIN_ 2 VIN+ 3 VSS 4 + 8 NC 7 VDD 6 VOUT 5 NC VOUT 1 VSS 2 VIN+ 3 4 VIN- + MCP6291 SOT-23-5 5 VDD MCP6291R SOT-23-5 VOUT 1 VIN+ 3 + VDD 2 5 VSS 4 VIN- MCP6292 PDIP, SOIC, MSOP VOUTA 1 VINA 2 VINA+ 3 VSS 4 _ 8 VDD -+ +7 VOUTB 6 VINB_ 5 VINB+ MCP6293 PDIP, SOIC, MSOP NC 1 VIN_ 2 VIN+ 3 VSS 4 + 8 CS 7 VDD 6 VOUT 5 NC VOUT 1 VSS 2 VIN+ 3 MCP6293 SOT-23-6 6 VDD 5 CS 4 VIN- + MCP6294 PDIP, SOIC, TSSOP VOUTA 1 VINA _ 14 VOUTD MCP6295 PDIP, SOIC, MSOP VOUTA/VINB+ 1 VINA_ 2 VINA+ 3 VSS 4 -+ +- 2 - + + - 13 VIND_ 12 VIND+ 11 VSS 10 VINC+ 8 VDD 7 VOUTB _ 6 VINB VINA+ 3 VDD 4 VINB+ 5 VINB_ 6 VOUTB 7 5 CS -+ +- 9 V _ INC 8 VOUTC 2004 Microchip Technology Inc. DS21812D-page 1 MCP6291/2/3/4/5 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VDD - VSS ........................................................................7.0V All Inputs and Outputs ................... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current ................................. Continuous Current at Input Pins ....................................................2 mA Current at Output and Supply Pins ............................30 mA Storage Temperature.....................................-65C to +150C Junction Temperature (TJ) . .........................................+150C ESD Protection On All Pins (HBM/MM) ................ 4 kV/400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 k to VDD/2 and VOUT VDD/2. Parameters Input Offset Input Offset Voltage Input Offset Voltage (Extended Temperature) Input Offset Temperature Drift Power Supply Rejection Ratio Input Bias Current At Temperature At Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode (Note 4) Common Mode Input Range Common Mode Rejection Ratio Common Mode Rejection Ratio Open-Loop Gain DC Open-Loop Gain (Large Signal) Output Maximum Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: 3: 4: VDD IQ 2.4 0.7 -- 1.0 5.5 1.3 V mA TA = -40C to +125C IO = 0 VOL, VOH ISC VSS + 15 -- -- 25 VDD - 15 -- mV mA AOL 90 110 -- dB VOUT = 0.2V to VDD - 0.2V, VCM = VSS (Note 1) VCMR CMRR CMRR VSS - 0.3 70 65 -- 85 80 VDD + 0.3 -- -- V dB dB VCM = -0.3V to 2.5V, VDD = 5V VCM = -0.3V to 5.3V, VDD = 5V VOS VOS VOS/TA PSRR IB IB IB IOS ZCM ZDIFF -3.0 -5.0 -- 70 -- -- -- -- -- -- -- -- 1.7 90 1.0 50 2 1.0 1013||6 1013||3 +3.0 +5.0 -- -- -- 200 5 -- -- -- mV mV V/C dB pA pA nA pA ||pF ||pF VCM = VSS (Note 1) TA = -40C to +125C, VCM = VSS (Note 1) TA = -40C to +125C, VCM = VSS (Note 1) VCM = VSS (Note 1) Note 2 TA = +85C (Note 2) TA = +125C (Note 2) Note 3 Note 3 Note 3 Sym Min Typ Max Units Conditions Input Bias, Input Offset Current and Impedance The MCP6295's VCM for op amp B (pins VOUTA/VINB+ and VINB-) is VSS + 100 mV. The current at the MCP6295's VINB- pin is specified by IB only. This specification does not apply to the MCP6295's VOUTA/VINB+ pin. The MCP6295's VINB- pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD - 100 mV. The MCP6295's VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. DS21812D-page 2 2004 Microchip Technology Inc. MCP6291/2/3/4/5 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters AC Response Gain Bandwidth Product Phase Margin at Unity-Gain Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- 3.5 8.7 3 -- -- -- VP-P nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 10 kHz f = 1 kHz GBWP PM SR -- -- -- 10.0 65 7 -- -- -- MHz V/s Sym Min Typ Max Units Conditions TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V and VSS = GND. Parameters Temperature Ranges Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 6L-SOT-23 Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note: JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- 256 230 85 163 206 70 120 100 -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W TA TA -40 -65 -- -- +125 +150 C C Note Sym Min Typ Max Units Conditions The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C. 2004 Microchip Technology Inc. DS21812D-page 3 MCP6291/2/3/4/5 MCP6293/MCP6295 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters CS Low Specifications CS Logic Threshold, Low CS Input Current, Low CS High Specifications CS Logic Threshold, High CS Input Current, High GND Current per Amplifier Amplifier Output Leakage Dynamic Specifications (Note 1) CS Low to Valid Amplifier Output, Turn-on Time CS High to Amplifier Output High-Z Hysteresis Note 1: tON -- 4 10 s CS Low 0.2 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.9 VDD/2, VDD = 5.0V CS High 0.8 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.1 VDD/2 VDD = 5V VIH ICSH ISS -- 0.8 VDD -- -- -- -- 0.7 -0.7 0.01 VDD 2 -- -- V A A A CS = VDD CS = VDD CS = VDD VIL ICSL VSS -- -- 0.01 0.2 VDD -- V A CS = VSS Sym Min Typ Max Units Conditions tOFF VHYST -- -- 0.01 0.6 -- -- s V The input condition (VIN) specified applies to both op amp A and B of the MCP6295. The dynamic specification is tested at the output of op amp B (VOUTB). CS VIL tON VIH tOFF Hi-Z VOUT Hi-Z ISS ICS -0.7 A (typ.) -1.0 mA (typ.) 0.7 A (typ.) 10 nA (typ.) -0.7 A (typ.) 0.7 A (typ.) FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6293 and MCP6295. DS21812D-page 4 2004 Microchip Technology Inc. MCP6291/2/3/4/5 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 12% 11% 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% 25% Percentage of Occurrences Percentage of Occurrences 840 Samples VCM = VSS 20% 840 Samples VCM = VSS TA = -40C to +125C 15% 10% 5% 0.0 0.4 0.8 1.2 1.6 2.0 2.4 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 2.8 0% 0 2 4 6 8 2600 2800 Input Offset Voltage (mV) -10 Input Offset Voltage Drift (V/C) FIGURE 2-1: 40% Input Offset Voltage. FIGURE 2-4: 30% Input Offset Voltage Drift. Percentage of Occurrences Percentage of Occurrences 35% 30% 25% 20% 15% 10% 5% 0% 210 Samples TA = 85C 25% 20% 15% 10% 5% 0% 210 Samples TA = +125C 1000 1200 1400 1600 1800 2000 2200 2400 0 10 20 30 40 50 60 70 80 90 100 Input Bias Current (pA) Input Bias Current (pA) FIGURE 2-2: TA = +85 C. 400 Input Bias Current at FIGURE 2-5: TA = +125 C. Input Bias Current at Input Offset Voltage (V) 350 300 250 200 150 100 50 0 -0.5 TA = -40C TA = +25C TA = +85C TA = +125C Input Offset Voltage (V) VDD = 2.4V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 800 VDD = 5.5V 750 700 650 600 550 500 450 400 350 300 250 200 -0.5 0.0 0.5 1.0 1.5 2.0 TA = +125C TA = +85C TA = +25C TA = -40C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.4V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. 2004 Microchip Technology Inc. DS21812D-page 5 3000 0 200 400 600 800 10 -8 -6 -4 -2 MCP6291/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 700 650 600 550 500 450 400 350 300 250 200 150 100 0.0 0.5 1.0 1.5 2.0 10,000 Input Offset Voltage (V) Input Bias, Offset Currents (pA) VCM = VSS Representative Part VCM = VDD VDD = 5.5V 1,000 100 Input Bias Current Input Offset Current VDD = 5.5V VDD = 2.4V 10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 25 35 45 55 65 75 85 95 105 115 125 Output Voltage (V) Ambient Temperature (C) FIGURE 2-7: Output Voltage. 110 100 Input Offset Voltage vs. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. 120 110 CMRR, PSRR (dB) 90 80 70 60 50 40 30 20 PSRR+ PSRR- CMRR PSRR, CMRR (dB) 100 CMRR 90 80 70 60 PSRR VCM = VSS 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1 10 100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (C) FIGURE 2-8: Frequency. 55 CMRR, PSRR vs. FIGURE 2-11: Temperature. 2.5 CMRR, PSRR vs. Ambient Input Bias, Offset Currents (pA) Input Bias, Offset Currents (nA) 45 35 25 15 5 -5 -15 -25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TA = +85C VDD = 5.5V Input Offset Current Input Bias Current 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 TA = +125C VDD = 5.5V Input Bias Current Input Offset Current 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85C. FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125C. DS21812D-page 6 2004 Microchip Technology Inc. MCP6291/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 1.6 1.4 1000 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TA = +125C TA = +85C TA = +25C TA = -40C Ouput Voltage Headroom (mV) Quiescent Current (mA/Amplifier) 100 10 VOL - VSS VDD - VOH 1 0.01 0.1 1 10 Power Supply Voltage (V) Output Current Magnitude (mA) FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. 120 100 Gain 80 Phase 60 40 20 0 -20 0.1 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. 16 90 85 GBWP, VDD = 5.5V GBWP, VDD = 2.4V 0 Gain Bandwidth Product (MHz) Open-Loop Gain (dB) -30 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 PM, VDD = 5.5V PM, VDD = 2.4V Open-Loop Phase () -60 -90 -120 -150 -180 1 10 100 1k -210 10k 100k 1M 10M 100M 1.E+08 75 70 65 60 55 50 125 Frequency (Hz) Ambient Temperature (C) FIGURE 2-14: Frequency. 10 Open-Loop Gain, Phase vs. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 12 10 Falling Edge, VDD = 5.5V VDD = 2.4V Maximum Output Voltage Swing (VP-P) Slew Rate (V/s) 8 6 4 2 0 Rising Edge, VDD = 5.5V VDD = 2.4V 1 VDD = 5.5V VDD = 2.4V 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 0.1 1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (C) FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-18: Temperature. Slew Rate vs. Ambient 2004 Microchip Technology Inc. DS21812D-page 7 Phase Margin () 80 MCP6291/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 1,000 11 Input Noise Voltage Density (nV/ Hz) Input Noise Voltage Density (nV/ Hz) 10 9 8 7 6 5 4 3 2 1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 f = 10 kHz VDD = 5.0V 100 10 1 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 0.1 1 10 100 1k 10k 100k 1M Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-19: vs. Frequency. 35 Input Noise Voltage Density FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 10 kHz. Channel-to-Channel Separation (dB) 140 Ouptut Short Circuit Current (mA) 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TA = +125C TA = +85C TA = +25C TA = -40C 130 120 110 100 1 10 100 Power Supply Voltage (V) Frequency (kHz) FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only). 1.6 1.2 Op-Amp shuts off here 1.0 VDD = 2.4V 1.4 Op-Amp turns on here Op Amp shuts off Op Amp turns on Hysteresis VDD = 5.5V Quiescent Current (mA/Amplifier) Quiescent Current (mA/Amplifier) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 CS swept high to low CS swept low to high 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Hysteresis CS swept high to low CS swept low to high 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Chip Select Voltage (V) FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6293 and MCP6295 only). DS21812D-page 8 2004 Microchip Technology Inc. MCP6291/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 5.0 4.5 G = +1V/V VDD = 5.0V 5.0 4.5 G = -1V/V VDD = 5.0V Output Voltage (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Output Voltage (V) 4.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Time (1 s/div) Time (1 s/div) FIGURE 2-25: Pulse Response. Large-Signal Non-inverting FIGURE 2-28: Response. Large-Signal Inverting Pulse G = +1V/V G = -1V/V Output Voltage (10 mV/div) Time (200 ns/div) Output Voltage (10 mV/div) Time (200 ns/div) FIGURE 2-26: Pulse Response. 3.0 Small-Signal Non-inverting FIGURE 2-29: Response. 6.0 Small-Signal Inverting Pulse Chip Select, Output Voltages (V) Chip Select, Output Voltages (V) 2.5 2.0 1.5 1.0 0.5 CS Voltage VDD = 2.4V G = +1V/V VIN = VSS 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 CS Voltage VDD = 5.5V G = +1V/V VIN = VSS VOUT Output On VOUT Output On Output High-Z 5.E-05 5.E-05 Output High-Z 0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 Time (5 s/div) Time (5 s/div) FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6293 and MCP6295 only). 2004 Microchip Technology Inc. DS21812D-page 9 MCP6291/2/3/4/5 3.0 PIN DESCRIPTIONS PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6291 (SOT-23-5) 1 4 3 5 2 -- -- MCP6271R (SOT-23-5) 1 4 3 2 5 -- -- MCP6293 (PDIP, SOIC, MSOP) 6 2 3 7 4 8 1,5 MCP6293 (SOT-23-6) 1 4 3 6 2 5 -- Symbol Description Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: MCP6291 (PDIP, SOIC, MSOP) 6 2 3 7 4 -- 1,5,8 VOUT VIN- VIN+ VDD VSS CS NC Analog Output Inverting Input Non-inverting Input Positive Power Supply Negative Power Supply Chip Select No Internal Connection TABLE 3-2: MCP6292 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- -- PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6294 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- -- MCP6295 -- 2 3 8 -- 6 7 -- -- -- 4 -- -- -- 1 5 Symbol VOUTA VINA- VINA+ VDD VINB+ VINB- VOUTB VOUTC VINC- VINC+ VSS VIND+ VIND- VOUTD VOUTA/VINB+ CS Analog Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) Analog Output (op amp A)/Non-inverting Input (op amp B) Chip Select Description 3.1 3.2 Analog Outputs Analog Inputs 3.4 CS Digital Input The output pins are low-impedance voltage sources. This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. 3.5 The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. Power Supply (VSS and VDD) 3.3 MCP6295's VOUTA/VINB+ Pin The positive power supply (VDD) is 2.4V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration). In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a local bypass capacitor (typically 0.01 F to 0.1 F) within 2 mm of the VDD pin. These parts need to use a bulk capacitor (within 100 mm), which can be shared with nearby analog parts. For the MCP6295 only, the output of op amp A is connected directly to the non-inverting input of op amp B; this is the VOUTA/VINB+ pin. This connection makes it possible to provide a Chip Select pin for duals in 8-pin packages. DS21812D-page 10 2004 Microchip Technology Inc. MCP6291/2/3/4/5 4.0 APPLICATION INFORMATION - RIN VIN MCP629X + VOUT The MCP6291/2/3/4/5 family of op amps is manufactured using Microchip's state-of-the-art CMOS process, specifically designed for low-cost, low-power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6291/2/3/4/5 ideal for battery-powered applications. 4.1 Rail-to-Rail Inputs ( Maximum expected V IN ) - V DD R IN -----------------------------------------------------------------------------------2 mA V SS - ( Minimum expected V IN ) R IN ---------------------------------------------------------------------------------2 mA The MCP6291/2/3/4/5 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal. 6 FIGURE 4-2: Resistor (RIN). Input Current Limiting 4.2 VDD = 5.0V G = +2V/V Rail-to-Rail Output Input, Output Voltage (V) 5 4 VIN 3 2 1 0 -1 -15 -14 -13 -12 -11 -10 -9 -8 VOUT The output voltage range of the MCP6291/2/3/4/5 op amp is VDD - 15 mV (min.) and VSS + 15 mV (max.) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-16 for more information. 4.3 Capacitive Loads -7 -6 -5 Time (1 ms/div) FIGURE 4-1: The MCP6291/2/3/4/5 Show No Phase Reversal. The input stage of the MCP6291/2/3/4/5 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM), while the other operates at high VCM. With this topology, the device operates with VCM up to 0.3 mV above VDD and 0.3 mV below VSS. The Input Offset Voltage (VOS) is measured at VCM = VSS - 0.3 mV and VDD + 0.3 mV to ensure proper operation. Input voltages that exceed the absolute maximum voltage (VSS - 0.3V to VDD + 0.3V) can cause excessive current to flow into or out of the input pins. Current beyond 2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 4-2. Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. - MCP629X VIN + RISO VOUT CL FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 2004 Microchip Technology Inc. DS21812D-page 11 MCP6291/2/3/4/5 100 Recommended RISO ( ) VOUTA/VINB+ VINB- 1 VINA- GN = 1 V/V GN 2 V/V 6 B MCP6295 5 7 2 3 A VOUTB VINA+ 10 10 100 1,000 10,000 Normalized Load Capacitance; CL/GN (pF) CS FIGURE 4-4: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6291/2/3/4/5 SPICE macro model are helpful. FIGURE 4-5: Cascaded Gain Amplifier. The output of op amp A is loaded by the input impedance of op amp B, which is typically 1013||6 pF, as specified in the DC specification table (Refer to Section 4.3 "Capacitive Loads" for further details regarding capacitive loads). The common mode input range of these op amps is specified in the data sheet as VSS - 300 mV and VDD + 300 mV. However, since the output of op amp A is limited to VOL and VOH (20 mV from the rails with a 10 k load), the non-inverting input range of op amp B is limited to the common mode input range of VSS + 20 mV and VDD - 20 mV. 4.4 MCP629X Chip Select (CS) The MCP6293 and MCP6295 are single and dual op amps with Chip Select (CS), respectively. When CS is pulled high, the supply current drops to 0.7 A (typ.) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier may not operate properly. Figure 1-1 shows the output voltage and supply current response to a CS pulse. 4.6 Supply Bypass 4.5 Cascaded Dual Op Amps (MCP6295) With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high-frequency performance. It also needs a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. The MCP6295 is a dual op amp with Chip Select (CS). The Chip Select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). This is available because the output of op amp A connects to the non-inverting input of op amp B, as shown in Figure 4-5. The Chip Select input, which can be connected to a microcontroller I/O line, puts the device in Low-power mode. Refer to Section 4.3 "MCP6293/5 Chip Select (CS)". 4.7 PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6291/2/3/4/5 family's bias current at 25C (1 pA, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-6. DS21812D-page 12 2004 Microchip Technology Inc. MCP6291/2/3/4/5 VIN- VIN+ 4.8 VSS Application Circuits MULTIPLE FEEDBACK LOW-PASS FILTER 4.8.1 The MCP6291/2/3/4/5 op amp can be used in activefilter applications. Figure 4-7 shows an inverting, thirdorder, multiple feedback low-pass filter that can be used as an anti-aliasing filter. Guard Ring R1 VIN C1 R3 C3 C4 R2 R4 VOUT FIGURE 4-6: for Inverting Gain. 1. Example Guard Ring Layout 2. For Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. MCP6291 VDD/2 FIGURE 4-7: Pass Filter. Multiple Feedback Low- This filter, and others, can be designed using Microchip's FilterLab(R) software, which is available on our web site (www.microchip.com). 4.8.2 PHOTODIODE AMPLIFIER Figure 4-8 shows a photodiode biased in the photovoltaic mode for high precision. The resistor R converts the diode current ID to the voltage VOUT. The capacitor is used to limit the bandwidth or to stabilize the circuit against the diode's capacitance (it is not always needed). C R VOUT ID light MCP6291 VDD/2 FIGURE 4-8: Photodiode Amplifier. 2004 Microchip Technology Inc. DS21812D-page 13 MCP6291/2/3/4/5 4.8.3 CASCADED OP AMP APPLICATIONS R4 R3 R2 R1 The MCP6295 provides the flexibility of Low-power mode for dual op amps in an 8-pin package. The MCP6295 eliminates the added cost and space in battery-powered applications by using two single op amps with Chip Select lines or a 10-pin device with one Chip Select line for both op amps. Since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with Chip Select line becomes suitable. The circuits below show possible applications for this device. A VIN MCP6295 B VOUT CS 4.8.3.1 Load Isolation FIGURE 4-10: Configuration. 4.8.3.3 Cascaded Gain Circuit With the cascaded op amp configuration, op amp B can be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low resistance loads in the feedback loop (such as an integrator circuit or filter circuit), the op amp may not have sufficient source current to drive the load. In this case, op amp B can be used as a buffer. Difference Amplifier Figure 4-11 shows op amp A as a difference amplifier with Chip Select. In this configuration, it is recommended to use well-matched resistors (e.g., 0.1%) to increase the Common Mode Rejection Ratio (CMRR). Op amp B can be used for additional gain or as a unitygain buffer to isolate the load from the difference amplifier. R4 R3 B A MCP6295 CS VOUTB Load VIN2 R2 R1 B A MCP6295 VOUT VIN1 R2 R1 FIGURE 4-9: Buffer. 4.8.3.2 Isolating the Load with a CS Cascaded Gain FIGURE 4-11: Difference Amplifier Circuit. Figure 4-10 shows a cascaded gain circuit configuration with Chip Select. Op amps A and B are configured in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp A is amplified by the gain of op amp A and B, as shown below: V OUT = V IN G A G B + V OSA G A G B + V OSB G B Where: GA = op amp A gain GB = op amp B gain VOSA = op amp A input offset voltage VOSB = op amp B input offset voltage Therefore, it is recommended to set most of the gain with op amp A and use op amp B with relatively small gain (e.g., a unity-gain buffer). DS21812D-page 14 2004 Microchip Technology Inc. MCP6291/2/3/4/5 4.8.3.4 Buffered Non-inverting Integrator 4.8.3.6 Figure 4-12 shows a lossy non-inverting integrator that is buffered and has a Chip Select input. Op amp A is configured as a non-inverting integrator. In this configuration, matching the impedance at each input is recommended. R F is used to provide a feedback loop at frequencies << 1/(2R1C1) and makes this a lossy integrator (it has a finite gain at DC). Op amp B is used to isolate the load from the integrator. R2 C2 RF VIN R1 A B R3 VOUT VIN C2 R5 R4 A R2 Second-Order MFB Low-Pass Filter with an Extra Pole-Zero Pair Figure 4-14 is a second-order multiple feedback lowpass filter with Chip Select. Use the FilterLab(R) software from Microchip to determine the R and C values for the op amp A's second-order filter. Op amp B can be used to add a pole-zero pair using C3, R6 and R7. R6 C1 C3 R1 R7 B VOUT MCP6295 C1 MCP6295 CS R1 C 1 = ( R 2 || R F )C 2 CS FIGURE 4-12: Buffered Non-inverting Integrator with Chip Select. 4.8.3.5 Inverting Integrator with Active Compensation and Chip Select FIGURE 4-14: Second-Order Multiple Feedback Low-Pass Filter with an Extra PoleZero Pair. 4.8.3.7 Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair Figure 4-13 uses an active compensator (op amp B) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. This circuit uses op amp B as a unity-gain buffer to isolate the integration capacitor C1 from op amp A and drives the capacitor with low-impedance source. Since both op amps are matched very well, they provide a high quality integrator. Figure 4-15 is a second-order, Sallen-Key low-pass filter with Chip Select. Use the FilterLab(R) software from Microchip to determine the R and C values for the op amp A's second-order filter. Op amp B can be used to add a pole-zero pair using C3, R5 and R6. R2 R1 R5 C3 R6 B VIN R1 C1 B A MCP6295 VOUT R4 VIN R3 C1 A VOUT MCP6295 C2 CS FIGURE 4-15: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. CS FIGURE 4-13: Compensation. Integrator Circuit with Active 2004 Microchip Technology Inc. DS21812D-page 15 MCP6291/2/3/4/5 4.8.3.8 Capacitorless Second-Order Low-Pass filter with Chip Select 5.0 DESIGN TOOLS The low-pass filter shown in Figure 4-16 does not require external capacitors and uses only three external resistors; the op amp's GBWP sets the corner frequency. R1 and R2 are used to set the circuit gain and R3 is used to set the Q. To avoid gain peaking in the frequency response, Q needs to be low (lower values need to be selected for R3). Note that the amplifier bandwidth varies greatly over temperature and process. However, this configuration provides a low cost solution for applications with high bandwidth requirements. R2 R3 A B VREF MCP6295 CS VOUT R1 Microchip provides the basic design tools needed for the MCP6291/2/3/4/5 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6291/2/3/4/5 op amps is available on our web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation at room temperature. See the macro model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. VIN 5.2 FilterLab(R) Software FIGURE 4-16: Capacitorless Second-Order Low-Pass Filter with Chip Select. Microchip's FilterLab software is an innovative tool that simplifies analog active-filter (using op amps) design. Available at no cost from our web site at www.microchip.com, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21812D-page 16 2004 Microchip Technology Inc. MCP6291/2/3/4/5 6.0 6.1 PACKAGING INFORMATION Package Marking Information 5-Lead SOT-23 (MCP6291 and MCP6291R) Example: Device Code CJNN EVNN XXNN MCP6291 MCP6291R CJ25 Note: Applies to 5-Lead SOT-23 6-Lead SOT-23 (MCP6283) Example: XXNN CM25 8-Lead MSOP XXXXXX YWWNNN Example: 6291E 436256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6291 E/P256 0436 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: MCP6291 E/SN0436 256 Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 2004 Microchip Technology Inc. DS21812D-page 17 MCP6291/2/3/4/5 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6294) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP6294-E/P 0436256 14-Lead SOIC (150 mil) (MCP6294) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6294ESL 0436256 14-Lead TSSOP (MCP6294) Example: XXXXXX YYWW NNN 6294EST 0436 256 DS21812D-page 18 2004 Microchip Technology Inc. MCP6291/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 D n 1 c A A2 L A1 Number of Pins Pitch p1 Outside lead pitch (basic) Overall Height A .035 .057 0.90 Molded Package Thickness A2 .035 .051 0.90 Standoff A1 .000 .006 0.00 Overall Width E .102 .118 2.60 Molded Package Width E1 .059 .069 1.50 Overall Length D .110 .122 2.80 Foot Length L .014 .022 0.35 Foot Angle 0 10 0 c Lead Thickness .004 .008 0.09 Lead Width B .014 .020 0.35 Mold Draft Angle Top 0 10 0 Mold Draft Angle Bottom 0 10 0 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Drawing No. C04-091 Units Dimension Limits n p MIN INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX MIN MILLIMETERS NOM 5 0.95 1.90 1.18 1.10 0.08 2.80 1.63 2.95 0.45 5 0.15 0.43 5 5 MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 2004 Microchip Technology Inc. DS21812D-page 19 MCP6291/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) E E1 B p1 D n 1 c A L A1 A2 Number of Pins Pitch p1 Outside lead pitch (basic) Overall Height A .035 .057 Molded Package Thickness .035 .051 A2 Standoff .000 .006 A1 Overall Width E .102 .118 Molded Package Width .059 .069 E1 Overall Length D .110 .122 Foot Length L .014 .022 Foot Angle 0 10 c Lead Thickness .004 .008 Lead Width B .014 .020 Mold Draft Angle Top 0 10 Mold Draft Angle Bottom 0 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 Units Dimension Limits n p MIN INCHES* NOM 6 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX MIN MILLIMETERS NOM 6 0.95 1.90 0.90 1.18 0.90 1.10 0.00 0.08 2.60 2.80 1.50 1.63 2.80 2.95 0.35 0.45 0 5 0.09 0.15 0.35 0.43 0 5 0 5 MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 DS21812D-page 20 2004 Microchip Technology Inc. MCP6291/2/3/4/5 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 A c A1 (F) A2 L 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness .000 .006 A1 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF 0 8 Foot Angle c Lead Thickness .003 .006 .009 .009 .012 .016 B Lead Width 5 Mold Draft Angle Top 5 15 5 5 15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Units Dimension Limits n p MIN INCHES NOM MAX MIN MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 - MAX 1.10 0.95 0.15 0.80 8 0.23 0.40 15 15 JEDEC Equivalent: MO-187 Drawing No. C04-111 2004 Microchip Technology Inc. DS21812D-page 21 MCP6291/2/3/4/5 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c L A1 eB B1 p B Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21812D-page 22 2004 Microchip Technology Inc. MCP6291/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2004 Microchip Technology Inc. DS21812D-page 23 MCP6291/2/3/4/5 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c eB A1 B1 B p L Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MIN MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 DS21812D-page 24 2004 Microchip Technology Inc. MCP6291/2/3/4/5 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 2004 Microchip Technology Inc. DS21812D-page 25 MCP6291/2/3/4/5 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 n B 1 A c L A1 A2 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 MIN INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 MAX MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21812D-page 26 2004 Microchip Technology Inc. MCP6291/2/3/4/5 APPENDIX A: REVISION HISTORY Revision A (June 2003) Original data sheet release. Revision B (October 2003) Revision C (June 2004) Revision D (December 2004) The following is the list of modifications: 1. 2. 3. 4. 5. Added SOT-23-5 packages for the MCP6291 and MCP6291R single op amps. Added SOT-23-6 package for the MCP6293 single op amp. Added Section 3.0 "Pin Descriptions". Corrected application circuits (Section 4.8 "Application Circuits"). Added SOT-23-5 and SOT-23-6 packages and corrected package marking information (Section 6.0 "Packaging Information"). Added Appendix A: Revision History. 6. 2004 Microchip Technology Inc. DS21812D-page 27 MCP6291/2/3/4/5 NOTES: DS21812D-page 28 2004 Microchip Technology Inc. MCP6291/2/3/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device - X /XX Package Examples: a) b) c) MCP6291-E/SN: MCP6291-E/MS: MCP6291-E/P: MCP6291T-E/OT: Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 5LD SOT-23 package. Temperature Range Device: MCP6291: MCP6291T: MCP6291RT: MCP6292: MCP6292T: MCP6293: MCP6293T: MCP6294: MCP6294T: MCP6295: MCP6295T: Single Op Amp Single Op Amp (Tape and Reel) (SOIC, MSOP, SOT-23-5) Single Op Amp (Tape and Reel) (SOT-23-5) Dual Op Amp Dual Op Amp (Tape and Reel) (SOIC, MSOP) Single Op Amp with Chip Select Single Op Amp with Chip Select (Tape and Reel) (SOIC, MSOP, SOT-23-6) Quad Op Amp Quad Op Amp (Tape and Reel) (SOIC, TSSOP) Dual Op Amp with Chip Select Dual Op Amp with Chip Select (Tape and Reel) (SOIC, MSOP) d) a) b) c) d) Extended Temperature, 8LD SOIC package. MCP6292-E/MS: Extended Temperature, 8LD MSOP package. MCP6292-E/P: Extended Temperature, 8LD PDIP package. MCP6292T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD SOIC package. MCP6293-E/MS: Extended Temperature, 8LD MSOP package. MCP6293-E/P: Extended Temperature, 8LD PDIP package. MCP6293T-E/CH: Tape and Reel, Extended Temperature, 6LD SOT-23 package. MCP6294-E/P: MCP6294T-E/SL: Extended Temperature, 14LD PDIP package. Tape and Reel, Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD TSSOP package. Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 8LD SOIC package. MCP6293-E/SN: MCP6292-E/SN: a) b) c) d) Temperature Range: E = -40C to +125C a) b) Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6291, MCP6291R) CH = Plastic Small Outline Transistor (SOT-23), 6-lead (MCP6293) MS = Plastic MSOP, 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC, (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4 mm Body), 14-lead c) d) a) b) c) d) MCP6294-E/SL: MCP6294-E/ST: MCP6295-E/SN: MCP6295-E/MS: MCP6295-E/P: MCP6295T-E/SN: Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com) to receive the most current information on our products. 2004 Microchip Technology Inc. DS21812D-page 29 MCP6291/2/3/4/5 NOTES: DS21812D-page 30 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS21812D-page 31 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205 ASIA/PACIFIC India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820 10/20/04 DS21812D-page 32 2004 Microchip Technology Inc. |
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